Mastech Digital is an IT Staffing and Digital Transformation Services company.

SOC Emulation Design Engineer

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Location: Phoenix, AZ
Job Code: 207706
Posted: Mar 25, 2020

Company Overview/ About Mastech Digital:
Mastech Digital is (NYSE American: MHH) is a leading provider of Digital Transformation IT Services. The Company offers Data Management and Analytics services; other digital transformation services that include, SAP HANA, and Digital Learning services, and IT staffing services. A minority-owned enterprise, Mastech Digital is headquartered in Pittsburgh, PA with offices across the U.S., Canada, and India.
As a $148M, NYSE-listed company with over 30 years of rich experience, we’ve become a key digital transformation partner for global corporations – from SMEs to Fortune 500 enterprises. Currently, Mastech Digital is hiring professionals for Fortune 100 Companies located in Bay Area, CA and Phoenix AZ.
Duration: 12+ Months Contract 
Location: Phoenix, AZ
Role: SoC Emulation Design Engineer/DFT Engineer 
Primary Skills: Infrastructure/Design Thinking
Role Description: 
The SoC Emulation Design Engineer/DFT Engineer would need to have at least 4+ years of experience. 
What we Offer:
- FORTUNE Magazine’s "100 Best Companies to Work For" in the Bay area CA and Phoenix AZ.
- Great Team and Work environment.
- All roles are Contract-to-Hire (performance based) – long-term engagement
- Sponsorship available.
- OPT can apply
Below are the positions open:
1. SoC Emulation Design Engineer
What Is Expected of You:

- Develop prototyping and emulation strategy, flow and environment setup
- Work closely with algorithm engineers, software engineers, architects and designers to quickly prototype new system and features
- Work closely with firmware and design verification engineers to assist software development and hardware verification
We're Looking For:
- Chip architecture, µArchitecture, design and design verification experience
- Performance modeling and evaluation
- Knowledge of OS kernel and experience in driver development
- Familiarity with IO's such as MIPI CSI & DSI, USB, PCIE, LPDDR
- Experience with CPU integration is a big plus, especially ARM/RISC-V CPU
- Capable of dealing with ambiguity with a fast changing consumer electronics field
- Results oriented, self-motivated, proactive with demonstrated creative & critical thinking
- Works effectively as an individual and in a multidisciplinary international team
- Knowledge of CoreSight/UltraSoC debug infrastructure integration is a plus
- System Level Modelling using System, TLM 2.0
- Experience working with Emulation Platforms (Zebu/Palladium/Veloce)
- Experience working on Virtual Platform / Hybrid modelling on Prototyping/Emulation systems
2. DFT Engineer
What Is Expected of You:

- Work with the Silicon teams to document the DFT specifications and define the requirements
- Develop and implement DFT architecture and infrastructure
- Develop and drive execution of enhanced DFX (DFT/Design-For-Debug) methodologies, with increased focus on debug support
- Work with the DV team to verify DFT implementations
- Generate structural test vectors, analyze and improve coverage/test time/test cost
- Work with designers on STA, physical, power and logical issues impacting DFT
- Work with test engineers to bring up test vectors on silicon
- Work with lab bring-up teams to bring up test vectors in the lab environment
- Manage schedules and support internal and external cross-functional/cross-organizational engineering efforts
We're Looking For:
- 4+ years of DFT experience
- Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time
- Experience in developing DFT specifications
- Knowledge of industry standard DFT and design tools
- Experience in debugging ATPG/MBIST patterns
- Knowledge of STA constraints and their interaction.
Preferred Qualifications: 
- Experience leading DFT efforts for large SOC designs
- Experience in driving DFT architecture and methods for designs
- Understanding of DV methodologies
- Ability to conduct experiments during silicon debug, gathering and analyzing data and utilize scripting to support efficient handling of ATE data
- Experience with STA constraints development and analysis for DFT modes
- Experience of running SDF simulations, and debugging failures
- Knowledge and experience of power-aware DFT, power delivery networks and their unique interaction with DFT architectures and implementations
- Experience with Analog DFT
- Experience with Protocol Oriented ATE testing
- Experience with System Verilog
Education: Bachelor’s degree in Computer Science, Electrical/Electronic Engineering, Information Technology or another related field or Equivalent.
Experience: Minimum 4+ years
Relocation: This position will not cover relocation expenses
Travel: No
Local Preferred: Yes
Recruiter Name: Himanshu Prashar
Recruiter Phone: 877 884 8834 (Ext: 2084)
Equal Employment Opportunity


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